Learn how to design a chip.
G mn5 Impletation end->mn5 mn0 Basics of Digital Logic mn0->start sn2 Clocks and STA mn0:e->sn2:w sn0 Logic Gates sn0:e->mn0:w sn1 Latches and Registers sn1:e->mn0:w mn1 Pick Up a Language mn1->mn0 sn5 System Verilog mn1:e->sn5:w sn3 Verilog sn3:e->mn1:w sn4 VHDL sn4:e->mn1:w mn2 Basics of Digital Design mn2->mn1 sn8 Async FIFO mn2:e->sn8:w sn6 Clock Domain sn6:e->mn2:w sn7 Memories sn7:e->mn2:w mn3 Verification mn3->mn2 sn11 Formal mn3:e->sn11:w sn12 DFT mn3:e->sn12:w sn9 UVM sn9:e->mn3:w sn10 Coverage sn10:e->mn3:w mn4 Synthesize mn4->mn3 sn15 Routing mn4:e->sn15:w sn16 ECO mn4:e->sn16:w sn13 Mapping sn13:e->mn4:w sn14 Placing sn14:e->mn4:w mn5->mn4 sn20 Clock Tree mn5:e->sn20:w sn21 Interconnection mn5:e->sn21:w sn17 Device Library sn17:e->mn5:w sn18 Layout sn18:e->mn5:w sn19 I/O sn19:e->mn5:w